This invention relates to flat panel displays, and more particularly to those which are addressed a line at a time and comprise an X-Y matrix array of field effect transistors (FETs).
In displays of this type, each FET is selectively operable by applying a potential across a unique pair of X and Y drive lines. This is to control activation of a unique optical transducer disposed at a unique coordinate location and constituting a corresponding single picture element. The respective transducers may use one of a variety of types of liquid crystals or electrochromic materials as the optically active medium.
It is imperative in devices of this matrix type that no defect exist which would create a short circuit between an X and a Y drive line, because this would cause all picture elements connected to either of these lines to be rendered inoperative. The most common cause of these unacceptable short-circuit-creating defects is a pinhole in the gate oxide insulator of the FET that controls activation of the associated transducer. Such short circuits are especially critical in FET flat panel displays because they may comprise an array of as many as five million FETs.
The probability of gate insulator pinholes could be reduced by increasing the gate oxide thickness or by adding to the gate oxide an additional layer of some other insulating material, such as phosphosilicate glass. Such approaches have the disadvantage of lowering the transconductance and increasing the threshold voltage of the FETs. While this would not be a serious problem for the FETs in the X-Y matrix because of their modest performance requirements, it is a problem for the drivers, shift registers, and other devices that make up the peripheral display circuitry and which must operate with higher currents and at higher speeds. If more processing steps are added to allow the gate insulator material of these two classes of devices to be different, the complexity of fabrication is undesirably increased.
No prior art known to applicants discloses or suggests the use of high value resistors in a flat panel FET matrix-type display device to minimize the effect of drive line short circuits caused by pinholes or other defects in the oxide insulation layers of the gate electrodes of the FETs. U.S. Pat. No. 3,655,996 disclosees a resistor in the line from an input source to the gate electrode of a FET to protect that FET against excessive forward voltage by passing current between the gate electrode and the source electrode. U.S. Pat. No. 3,754,171 also teaches the use of a protective resistor in the gate circuit of a FET. U.S. Pat. Nos. 4,027,173 and 4,209,713 teach the use of a resistor in the input circuit to the gate electrode of a FET to protect that FET by serving as a current limiting means. Thus all prior art FET devices known to applicants employ a resistor in the gate circuit to protect a specific FET.